Senior Digital Design Verification Engineer
Vor 5 Tagen
IC Resources is seeking a highly skilled Senior Digital Design Verification Engineer to join our team. As a key member of our R&D team, you will be responsible for leading hands-on verification duties, setting up, defining, and developing existing and new processes.
Key Responsibilities- Implement the UVM verification methodology and execute the verification plan to ensure that processors/SoCs deliver industry-defining performance.
- Develop and maintain a strong understanding of system verilog, C/C++/system C, and UVM test benches.
- Collaborate with cross-domain teams and interact with customers to deliver successful silicon SoCs with embedded processor cores and proven IP.
- Take ownership of innovative projects and contribute to the realization of landmark products and company goals.
- 10+ years' industry experience in SoC design verification, system verilog languages (UVM, SVA, SFC), low power verification (UPF methodology), software/hardware co-verification (System C/C/C++).
- Strong track record of being a hands-on, involved engineering team player who delivered successful silicon SoCs with embedded processor cores and proven IP.
- Excellent communication and interpersonal skills, with the ability to interact with customers and cross-domain teams.
- Enthusiasm for taking ownership and contributing to innovative projects.
- Embedded SoC development, processes, and delivery.
- Formal verification, Jasper, SVA, assertions.
- Proven experience in IP delivery, usage, and insightfully hands-on with industry-standard EDA flows and methodologies.
- Digital design with VHDL, Verilog, System Verilog.
- Confident scripting experience in Python, C, C++, System C, and TcL.
- Automation processes, CI/CD, and DevOps, including Git/GitHub.
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Senior Digital Design Verification Engineer
Vor 5 Tagen
Neuenburg, Neuenburg, Schweiz IC Resources VollzeitAbout the RoleIC Resources is seeking a highly skilled Senior Digital Design Verification Engineer to join our team. As a key member of our R&D team, you will be responsible for leading hands-on verification duties, setting up, defining, and developing existing and new processes.Key ResponsibilitiesImplement the UVM verification methodology and execute the...
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