STA/Timing Engineer
vor 4 Wochen
We are seeking an experienced STA/Timing Engineer to join our client in Lausanne. This is an exciting opportunity to work with a fabless Semiconductor company that specializes in high-speed bus transfer in wireless communications.
The company has several sites across and is now looking to grow its Physical Design team. As a STA/Timing Engineer, you will be responsible for designing and verifying complex digital circuits, ensuring they meet the required timing and performance specifications.
Key Responsibilities:
- Design and verification of digital circuits using EDA tools such as Tempus, Genus, and LEC
- Development of SDC constraints and timing analysis
- Collaboration with cross-functional teams to ensure successful tapeouts
- Proven experience in 7+ successful tapeouts
Requirements:
- Experience with block and chip level STA
- Good knowledge of the complete RTL-GDS flow
- Experience with EDA tools such as Tempus, Genus, and LEC
About the Company:
Our client is a pre-IPO company that specializes in high-speed bus transfer in wireless communications. They have sites in Germany and the UK and are happy for Engineers to be based at one of these sites if preferred.
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