STA/Timing Engineer

vor 4 Monaten

Lausanne, Schweiz IC Resources Vollzeit
STA/Timing Engineer – Lausanne

I am looking for an STA/Timing Engineer to come and join a client in Lausanne. This is an exciting opportunity to join a fabless Semiconductor company that has several sites across and is now looking to grow its Physical Design team.

They are a pre-IPO company that specialises in high-speed bus transfer in wireless communications and are already challenging established tech giants within the industry.

This client also has sites in Germany and the UK and is happy for Engineers to be based at one of these sites if preferred.

Requirements:
  • Experience with block and chip level STA
  • Good knowledge of the complete RTL-GDS flow
  • Experience with SDC constraints
  • Experience with EDA tools such as Tempus, Genus and LEC
  • Proved experience in 7+ successful tapeouts
If you are interested in finding out more about this opportunity or others then please contact Jordan Browne

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