Senior Analog IC Layout Engineer – Hybrid
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IC Resources seeks a Senior IC Layout Engineer to join their semiconductor team in Lausanne. The role offers hybrid working, with 3 days per week in the office, and focuses on analog layout and physical verification for high-speed designs.
You will develop custom analog layouts, work on multi-Gigabit SerDes and memory interfaces, apply advanced layout techniques, and use Cadence Virtuoso, Calibre and PVS. Visa sponsorship and relocation support are available where required.
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