Senior ASIC Physical Layout Engineer
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Senior ASIC Physical Layout Engineer
Location: Lausanne Area / Western Switzerland (Flexible working culture)
Permanent Position
Are you an experienced Layout Engineer looking to work on cutting-edge mixed-signal ASICs that push the boundaries of ultra-low-power technology?
I'm currently supporting a highly respected Swiss technology organization in their search for a Senior ASIC Physical Layout Engineer to join an experienced multidisciplinary IC design team developing next-generation semiconductor solutions.
This is an opportunity to work somewhere that combines the technical challenges of advanced R&D with the stability and long-term vision of an established organization.
What you will be working on
- Lead top-level physical layout integration for advanced mixed-signal ASICs
- Drive floorplanning, chip finishing and physical verification through to successful tape-out
- Solve complex DRC/LVS/ERC challenges across advanced CMOS technologies
- Collaborate closely with Analog, RF, Digital and System Designers
- Contribute to ultra-low-power SoCs, imaging devices and advanced RF technologies
- Help shape physical design methodologies and layout best practices
What we're looking for:
- Strong experience delivering full-chip or top-level IC layout
- Expertise with Cadence Virtuoso (Virtuoso XL)
- Strong hands-on experience using Siemens Calibre (DRC/LVS/ERC)
- Experience with mixed-signal, Analog and/or RF ASICs
- Knowledge of advanced CMOS technologies
- Proven experience supporting successful tape-outs
- Experience resolving complex LVS issues and top-level integration is highly valued
- Strong English communication skills
Nice to have:
- Ultra-Low Power (ULP) design
- FinFET technologies
- Advanced process nodes
- ESD / Latch-up expertise$
- RF layout optimization
Why consider this opportunity?
- Work on genuinely innovative semiconductor technology
- Join an internationally recognized Swiss engineering organization
- Long-term permanent position
- Collaborative, highly technical environment
- Excellent work-life balance
- Opportunity to influence future IC development
- Relocation support available for suitable candidates
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