Digital Design Verification Engineer

Vor 2 Tagen

Zürich, Zürich, Schweiz Umbilical Advanced Vollzeit

Join an innovative semiconductor company developing high-performance digital and mixed-signal solutions. As a Digital Design & Verification Engineer, you'll take ownership of designing, integrating, and verifying complex digital IP within a modern SoC environment.

What You'll Do

  • Develop high-quality, synthesis-ready SystemVerilog RTL for a range of digital components, including control logic, AMBA-based bus interfaces (AXI/AHB/APB), FIFOs, arbitration units, DMA engines, and data-path elements.
  • Apply industry-standard power-aware design techniques and optimise across performance, power, and area within modern ASIC design flows.
  • Build and maintain UVM verification environments -agents, sequencers, predictors, scoreboards -and drive verification to functional, code, and assertion coverage targets.
  • Run gate-level simulations with SDF for timing-critical scenarios and support FPGA-based prototypes to accelerate system-level validation.
  • Work closely with cross-functional teams spanning RTL design, verification, physical design, and software to ensure robust IP delivery and seamless SoC integration.

What You'll Need

  • Experience in ASIC digital design or verification, with strong SystemVerilog RTL proficiency and practical UVM exposure.
  • Experience with mainstream processor architectures (such as ARM or RISC-V) at either IP integration or subsystem design level.
  • Understanding of synthesis principles and the relationship between coding style and timing/power/area results.
  • Strong communication skills and a methodical approach to developing reusable design and verification assets.
  • In an ideal world - experience working on memory-related IP (SRAM controllers, peripheral logic, MBIST/scan) and knowledge of UPF or similar power-aware methodologies.
  • Exposure to GLS/SDF flows, FPGA prototyping, and hardware/software co-validation.

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