Senior Digital Verification Engineer
vor 1 Monat
We are seeking a highly skilled Digital Verification Engineer to join our team at onsemi. As a key member of our verification team, you will be responsible for defining the digital verification strategy and detailed verification plans for our mixed-signal System-on-Chips (SoCs).
Key Responsibilities
- Develop and lead the verification activities in project teams.
- Create SystemVerilog/UVM test environments for top-level SoCs.
- Write scripts to automate test procedures and debug functional errors in RTL.
- Perform formal verification and work with colleagues to improve digital verification methodology.
Requirements
- Minimum MS in electrical engineering, microelectronics, or related technical field.
- Minimum 8 years of digital verification experience.
- Solid understanding of verification best practices, including verification planning, requirements tracking, and functional coverage.
- In-depth knowledge of state-of-the-art verification methodologies, such as UVM, formal verification, and constrained random driven verification.
- Programming skills in embedded C and Python.
- Excellent English written and verbal communication skills.
- Eligibility to work in Switzerland.
What Else You May Bring
- Experience with project technical leadership and verification of complex multi-processor systems.
- Knowledge of French.
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