Advanced IC Verification Specialist

vor 2 Wochen


MarinEpagnier, Neuenburg, Schweiz Onsemi Vollzeit

**About Onsemi**


At Onsemi, we strive to improve lives every day through our innovative silicon solutions. Our intelligent power and sensing technologies address the world's most complex challenges, driving the creation of a safer, cleaner, and more connected world. Our team in Marin/Switzerland develops cutting-edge digital signal processing systems, secure Bluetooth-enabled MCUs, and highly reliable mixed-signal System-on-Chips (SoCs) that sense and connect the world or help manage personal health through wearable or implantable devices.


**The Role**


As part of the Sensor Interface Division, the Low-Power Sensing Team in Marin is expanding its design team with a Senior Digital IC Verification Engineer who possesses technical leadership skills. You will lead the development of UVM test environments for our leading-edge ultra-low power ICs.


**Why Work with Us**


We foster a diverse, inclusive, and socially responsible environment where our employees can transform their tomorrow. If you're passionate about shaping a better future, join us and define your future.


**Responsibilities**



  • Define the digital verification strategy and detailed verification plans for our mixed-signal System-on-Chips (SoCs).
  • Coordinate/lead the verification activities in the project teams.
  • Develop SystemVerilog/UVM test environments for top-level SoCs.
  • Write scripts to automate test procedures.
  • Debug functional errors in RTL.
  • Perform formal verification.
  • Collaborate with colleagues in other countries to enhance the digital verification methodology.

**Requirements**


* Minimum MS in electrical engineering, microelectronics, or a related technical field.

Minimum 8 years of digital verification experience.
Solid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage.
In-depth knowledge and some years of proven experience in state-of-the-art verification methodologies (UVM, formal verification), constrained random-driven verification, assertion-based verification, test environment architecture & creation, regression management, coverage collection.
Programming skills – embedded C, Python.
Excellent English written and verbal communication skills.
Eligibility to work in Switzerland.


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