Senior ASIC Hardware Engineer – Physical Implementation
Vor 2 Tagen
Senior ASIC Hardware Engineer – Physical Implementation & Sign-Off We are supporting a cutting‑edge technology company in Zürich that is seeking a motivated Senior ASIC Hardware Engineer who can take ownership of advanced physical design challenges either from a Timing Closure angle or a Power Integrity / IR‑Drop perspective. This is a full‑time permanently employed position. What this role is about: You will play a key role in the sign‑off of complex IP and SoC blocks, working with both digital backend and full‑custom teams. Depending on your strengths, you could focus more on: Timing Closure & STA Power Integrity, IR Drop & EM Both skill sets are equally welcome; the company will adapt the role to the strengths of the right engineer. What you will be doing: If your strength is Timing Closure: Building, refining & maintaining timing constraints (clocks, I/O timing, exceptions) Running STA across corners/modes & landing reliable setup/hold closure Collaborating with synthesis, P&R & clock‑tree teams to guide design decisions Debugging skew/jitter issues & improving clocking strategy Leading functional & timing ECO loops to convergence Supporting GLS, SDF, and verification teams with timing data If your strength is IR / Power Integrity: Planning & reviewing power grids (straps, taps, decaps, via strategy) Running IR drop & EM analysis throughout the flow (early + post‑route) Identifying hot spots and driving actionable fixes Working with RTL, layout, and timing teams to improve robustness Generating SAIF/VCD activity & validating realistic workloads Enhancing power‑analysis flows with automation & reproducible scenarios For both profiles: Collaborating closely with custom‑design, digital, backend & verification teams Ensuring smooth integration of custom macros into digital flows Improving automation using Python or Tcl Contributing to first‑time‑right tapeouts on modern technology nodes Who will thrive in this role You don't need to be an expert in both timing and IR drop but you must be strong in at least one. What the company is looking for: 5+ years of experience in ASIC backend / physical design Hands‑on exposure to STA, P&R, CTS, ECO loops, or IR‑drop/EM analysis Experience working from synthesis route sign‑off Understanding of how physical choices impact timing, power & reliability Ability to interpret reports and quickly turn them into practical fixes Experience on advanced nodes (sub‑14nm) is a plus Confident scripting in Tcl or Python A collaborative mindset & clear documentation habits Experience with power‑gated designs, multi‑voltage flows, thermal considerations, scan/MBIST, or large hierarchical SoC closure is advantageous. Backgrounds that fit well SoC design houses Accelerator / AI hardware companies Memory or custom‑silicon teams Seniority level Not Applicable Employment type Full‑time Job function Information Technology Industries Technology, Information and Media #J-18808-Ljbffr
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Senior ASIC Physical Design
Vor 2 Tagen
Zürich, Schweiz TalentCloud Group Recruitment VollzeitA leading technology firm in Zürich is looking for a Senior ASIC Hardware Engineer to tackle advanced physical design challenges. With a focus on either Timing Closure or Power Integrity, you'll sign off on complex IP and SoC blocks while collaborating with various engineering teams. Strong experience in ASIC backend design and knowledge of physical...
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ASIC Physical Design Lead
Vor 7 Tagen
Zürich, Zürich, Schweiz Umbilical Advanced Vollzeit CHF 120'000 - CHF 180'000 pro JahrJoin a leading semiconductor company developing advanced mixed-signal SoCs. As aTechnical Lead – ASIC Physical Design, you'll own the RTL-to-GDSII flow for complex IP and subsystems while building and leading a high-performing backend team.What You'll DoLead the full RTL-to-GDSII implementation flow, including synthesis, floorplanning, place-and-route,...
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Senior Algorithms Engineer – PHY
Vor 7 Tagen
Zürich, Zürich, Schweiz IC Resources Vollzeit CHF 90'000 - CHF 120'000 pro JahrA Senior Algorithms Engineer – PHY /5G is urgently sought by this leader in the development of wireless communication products to be based at their R+D Centre in Zurich. The Senior Algorithm Engineer – PHY 5G will be designing new algorithms and architectures for 3GPP NR/LTE based products.The Senior Algorithm Engineer – PHY 5G will be working with...
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Senior Physical Design Engineer
Vor 7 Tagen
Zürich, Zürich, Schweiz IC Resources Vollzeit CHF 120'000 - CHF 180'000 pro JahrOur client, a cutting-edge semiconductor company working on next-generation compute architectures, is looking for a Senior Physical Design Engineer to take ownership across complex IP and SoC designs. This is a key technical role focused on high-quality implementation, collaboration, and delivering robust silicon on advanced process nodes.As a Senior...
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Senior Digital Hardware Engineer
Vor 6 Tagen
Zürich, Schweiz TalentCloud Group VollzeitSenior Digital Hardware Engineer (RTL & Verification) Zurich | Hybrid We are supporting one of our Swiss technology partners in their search for a Senior Digital Hardware Engineer to strengthen their growing silicon team in Zürich. This is a permanent role, is ideal for someone who enjoys owning IP blocks end-to-end, thrives in cross-functional...
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Digital Design Verification Engineer
vor 3 Wochen
Zürich, Schweiz Umbilical Advanced VollzeitSenior Digital IC Design/Verification Engineer Join an innovative semiconductor company developing high-performance digital and mixed-signal solutions. As a Digital Design & Verification Engineer, you’ll take ownership of designing, integrating, and verifying complex digital IP within a modern SoC environment. What You’ll Do Develop high-quality,...
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Senior Engineer – Backend
vor 4 Wochen
Zürich, Schweiz Synthara AG VollzeitLocation: Zürich, Switzerland Seniority: 5+ years (physical design with a timing focus) Own timing closure and sign-off for complex IP and SoC blocks that integrate our full-custom ComputeRAM® macros. You will drive Static Timing Analysis across corners and modes, shape clean constraints, partner closely with synthesis, place-and-route, and clock-tree...
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Zürich, Schweiz TalentCloud Group VollzeitA Swiss technology partner is seeking a Senior Digital Hardware Engineer in Zürich. The role involves creating and validating complex digital IPs within advanced compute platforms, utilizing SystemVerilog RTL. Candidates should have over 5 years of experience in digital design or verification with solid knowledge of synthesis concepts. This permanent...
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Senior Digital IC Design
vor 3 Wochen
Zürich, Schweiz Umbilical Advanced VollzeitA semiconductor technology company located in Zürich is seeking a Senior Digital IC Design/Verification Engineer to design and verify complex digital IP within a modern SoC environment. This role requires strong skills in SystemVerilog and UVM, as well as a background in ASIC design. Candidates should have experience with processor architectures like ARM or...
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Senior C++ Engineer
vor 3 Wochen
Zürich, Schweiz Selby Jennings VollzeitSenior C++ Engineer - Hardware / Low-Latency Trading Systems (HFT) Location: Zurich (on-site). Kindly note that sponsorship is not available for this role. EU citizens or individuals with existing Swiss/EU work authorisation are welcome to apply. A leading high-frequency trading firm is seeking a Senior C++ Engineer to join its low-latency trading desk. This...
