ASIC Physical Design Lead

Vor 3 Tagen

Zürich, Zürich, Schweiz Umbilical Advanced Vollzeit CHF 120'000 - CHF 180'000 pro Jahr

Join a leading semiconductor company developing advanced mixed-signal SoCs. As a
Technical Lead – ASIC Physical Design
, you'll own the RTL-to-GDSII flow for complex IP and subsystems while building and leading a high-performing backend team.

What You'll Do

  • Lead the full RTL-to-GDSII implementation flow, including synthesis, floorplanning, place-and-route, clock tree synthesis, routing, extraction, and timing closure.
  • Define and maintain physical design methodology, constraints, and quality metrics.
  • Set and track PPA (performance, power, area) targets, ensuring correlation across design stages.
  • Integrate custom macros, SRAMs, and analog IP into digital-on-top mixed-signal designs.
  • Implement low-power design intent using UPF/CPF, including isolation, retention, and power-aware analysis.
  • Collaborate with DFT and RTL teams to ensure testable, sign-off-ready designs.
  • Automate flows using Tcl/Python and build reproducible CI/CD environments.
  • Recruit, mentor, and develop a backend team with clear ownership areas.
  • Engage with foundries for PDK updates, rule compliance, and reliability guidance.

What You'll Need

  • 8+ years in ASIC physical design, including 2+ tapeouts as design owner.
  • Strong experience with Synopsys or Cadence RTL-to-GDSII tool flows.
  • Expertise in timing closure, multi-corner/multi-mode (MCMM) STA, and power optimization.
  • Proficiency in floorplanning, hierarchical integration, and IR/EM analysis.
  • Knowledge of UPF/CPF for multi-voltage, power-gated designs.
  • Scripting skills (Tcl, Python) and familiarity with version control.
  • Ability to lead a team while remaining hands-on on complex design tasks.

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