Senior Layout Engineer

vor 11 Stunden

Zürich, Zürich, Schweiz IC Resources Vollzeit

My client is seeking a highly skilled and experienced
Senior Analog IC Layout Engineer
to join their innovative team in Zürich, Switzerland. This role is ideal for a professional with over 5 years of experience in custom analog, SRAM, and custom-digital layout. You will play a critical role in designing and implementing transistor-level and block-level custom layouts for mixed-signal, SRAM, and custom-digital IP. This is an exciting opportunity to work on cutting-edge technologies, including advanced nodes down to 4 nm and below, and contribute to the development of industry-leading solutions.

Responsibilities
As a Senior Analog IC Layout Engineer, your key responsibilities will include:

  • Planning and implementing full-custom layouts for standard cells, custom datapaths, and SRAM periphery/arrays
  • Driving and providing feedback to the design team to achieve the most power-efficient design layout possible
  • Collaborating with schematic owners to align on constraints, define pins/abstracts, LEF views, keep-outs, and tiling for memory-like macros, and coordinate with MBIST/scan wrappers and test hooks
  • Automating and documenting processes by maintaining checklists, templates, and layout guidelines, as well as scripting repetitive tasks using TCL or Python.
  • Ensuring successful tape-in and silicon of custom blocks or macros with clean DRC/LVS/PEX and correlated post-silicon parasitics, while delivering comprehensive reports and lessons learned

Qualifications
To excel in this role, you should possess the following qualifications:

  • A minimum of 5 years of experience in custom layout for analog, SRAM, or custom-digital IP, with a proven track record of ownership from floorplan to sign-off
  • Demonstrated expertise in sub-28 nm nodes, including practical knowledge of FinFET/FDSOI, multi-patterning/EUV constraints, and coloring
  • Proficiency in analog layout techniques such as common-centroid, interdigitation, current-mirror symmetry, matched routing, shielding/guard rings, and substrate noise isolation
  • A solid understanding of timing, IR, and EM implications of layout, with the ability to read extraction/timing reports and collaborate with designers, PD, and STA teams
  • Strong communication skills, rigorous documentation practices, and a collaborative mindset to work effectively across custom design, digital, and backend teams

Why join them?
This is a unique opportunity to work on groundbreaking technologies and contribute to the development of innovative solutions in the field of analog IC layout engineering. You will collaborate with a team of talented professionals and have the chance to make a significant impact on the success of our projects.

If you are passionate about cutting-edge technology and possess the skills and experience required for this role, we encourage you to apply and become a part of our dynamic team.

For more information and to apply, please contact Ane @ IC Resources with your CV and a time for a short initial call

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