Asic Digital Designer

**Company Description**
**Job Description** Introduction**

**Functions**

As an ASIC Digital Designer you will:

- Perform full-chip digital integration and verification:

- incorporate custom logic, third party IP blocks and standard interfaces
- manage clock/reset domains
- Develop RTL code ensuring synthesizable and reusable designs.
- Develop high level architectures for ASIC designs, including SoC partitioning, data paths, control logic and interfaces.
- Write testbenches and run simulations to verify design functionality.

**Qualifications**
Master's degree or PhD or equivalent relevant experience in the field of Electronics Engineering or a related field.

**Experience**:
The experience required for this post is:

- Demonstrated experience in hierarchical Digital-On-Top ASIC integration and implementation (from RTL to GDS) including functional and physical verification.
- Proven experience with advanced EDA tools and deep submicron CMOS technologies, including Cadence tools and process nodes such as 65nm, 28nm, or smaller.
- Experience in RTL design (Verilog/SystemVerilog) and scripting languages (Python, TCL, and Shell) for workflow automation.
- Experience in performing, Logic Synthesis, Timing Closure, Static Timing Analysis, and Power Integrity Analysis.
- Experience in physical design floor planning, cell placement, routing and sign-off checks (DRC, LVS).
- Experience in developing test benches for conducting behavioural and functional simulations.
- Knowledge in integrating Analog and Digital IPs, managing interconnects, planning clock/reset domains and assigning timing constraints.
- Knowledge in integrating design-for-testability (DFT) structures (scan chains, BIST, JTAG) and employing design-for-manufacturing (DFM) methodologies.

Experience in the following fields will also be valued:

- Understanding of System-on-Chip (SoC) design techniques, including bus protocols (AXI, AHB, APB).
- Knowledge of RISC-V ISA and experience with RISC-V core integration.
- Experience with Microarchitecture design: fSMs, pipelining, ALUs, memory controllers.
- Experience with Debugging and linting tools (Verilator, etc.).
- Experience with FPGA prototyping for SoC validation.
- Experience in the use of design methodologies for the mitigation of radiation effects (SEE and TID) in digital CMOS circuits.

**Technical competencies**:

- Design and simulation of digital microelectronic circuits.
- Testing and measurement of digital microelectronic circuits.

**Behavioural competencies**:

- Working in Teams: understanding when teamwork is required to achieve the best results; including others accordingly and sharing information.
- Achieving Results: having a structured and organised approach towards work; being able to set priorities and plan tasks with results in mind.
- Demonstrating Flexibility: adapting quickly and resourcefully to shifting priorities and requirements.
- Communicating Effectively: checking to ensure that the message has been well understood. Ensuring that information, procedures and decisions are appropriately documented.
- Learning and Sharing Knowledge: keeping up-to-date with developments in own field of expertise and readily absorbing new information; sharing knowledge and expertise freely and willingly with others; coaching others to ensure knowledge transfer.

**Language skills**:
Spoken and written English, with a commitment to learn French.
**Additional Information** Eligibility and closing date**:
**Employment Conditions**

Working Hours: 40 hours per week

This position involves:

- Work in Radiation Areas.
- Work during nights, Sundays and official holidays, when required by the needs of the Organization.

Job grade: 6-7

Job reference: EP-ESE-ME-2025-85-LD

Benchmark Job Title: Electronics Engineer