SoC - ASIC Design Manager

vor 2 Wochen


Neuenburg, Schweiz TN Switzerland Vollzeit

Brand new role for a well-established player in the Semiconductor industry - based full-time in Switzerland.

Salary is negotiable - (based on seniority and relevance of experience) - circa 100-150k CHF plus package

I am looking for a SOC Design Manager; to be responsible for the end-to-end design, set-up, micro-architecture definition, definition of the whole process & design flow, and RTL design of digital-analog-mixed signal / AMS chip development and delivery projects.

As SOC Design Manager, your duties will include team leadership / management of a multi-functional and skilled team in charge of delivering the full chip to delivery at the fab.

Must have experience:

  1. Degree / Masters / PhD in electronics / micro-electronics, physics or similar field
  2. 10-15+ years' experience of full chip design and delivery
  3. Tech lead / team leadership / team management
  4. Digital / AMS, analog-mixed-signal IP, chips and SOCs
  5. ASIC & FPGA - verilog, system verilog, VHDL
  6. ADC / DAC - digital - analog interfaces
  7. Functional verification - system verilog - IP, system, sub-system, block, top level experience
  8. Creation of test-benches
  9. detailed knowledge of complex tape-out processes, and interactions with fabrication plants
  10. Full digital design flow, from RTL to GDS
  11. SOC design, integration, system design, system architecture
  12. power management / PMIC / ultra-low power / optimisation & performance
  13. synthesis / HLS / STA
  14. physical implementation / physical design
  15. Understanding of software / firmware / embedded requirements

Bonus / nice to have skills:

  1. PLLs / filter design
  2. RF-SOC
  3. DSP, signal processing
  4. Flash memory - DDR / HBM / high-bandwidth memory / cache coherency
  5. clock, timing constraints

This position is ONLY available to senior level digital / AMS design managers with SOC design, delivery and management experience.

MUST HAVE - EU working rights.

#J-18808-Ljbffr
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