Process Engineer

My client’s “Integrated & Wireless Systems” Business Unit based in Neuchâtel, Switzerland, is currently looking for a CAD Layout R&D Engineer.

About the company's mission and values:

Their mission is the development and transfer of innovative technologies to the Swiss industry. The objective is to make an impact on our customers and on society at large in the fields of precision manufacturing, digital technologies, and sustainable energy. Their strength is the excellence of their people, passionate specialists dedicated to innovation and technology transfer. They believe that strong values support the successful development of our organization as well as the harmonious and balanced development of all their employees.

About the role:

As a CAD Layout R&D Engineer, you will play an important role within the SwissChips initiative to boost the Swiss chip industry. You will provide highly competitive analog CAD & layout solutions meeting project requirements to maximize design/methodology reusability among projects and ensure on-time & quality deliveries. You will also execute and support design and layout engineering activities across a range of projects targeting various mainly CMOS process nodes, spanning from 0.18um to 22nm and below.

RESPONSIBILITIES:

CAD (~30%):

• EDA Back-End Analog (Cadence & Siemens): installation, customization, update, support & technology watch.
• Develop automation to improve designer efficiency. Put in place and test design flow.
• Provide technical support to the design team.
• Technology watch – flows and tools including AI for CAD.
• Participate in PDK validation: Assess, configure, and manage deployment of multiple Process Design Kits.
• Participate in External IP/Libraries: installation, customization, update & support.
• Maintain Libraries & Analog IP DB: customization, update, support.

Layout (~70%):

• Keep hands-on layout experience in IC projects.
• IC layout task execution including acceptance for integration & tape out.
• Support project managers & designers in the layout task definition & execution (preparation, resources, effort, and schedules).
• Actively participate in projects to smooth IC layout outsourcing execution and ensure that work quality is met upon company flow and using their methodology.
• Support Group Leader and participate in IC layout & tape out resource planning.
• Maintain IC layout expertise & state-of-the-art techniques for very advanced CMOS nodes & foundries, including mastering process features/options.
• Ensure that layout work quality is met upon company IC design/quality flow.

Required Experience:

• At least a BS in Electrical Engineering and 3+ years of industrial experience with CAD tools and layout.
• Experience in Linux.
• Experience in EDA Front-End Analog is a plus.
• Experience in advanced CMOS processes (such as 22nm) is a plus.
• Experience in analog/RF IC design is a plus.
• CAD tools including Cadence and Mentor for analog design and layout.
• Good programming skills in scripting languages (shell/bash/Python/Skill scripting).
• Experience with SVN and/or other design version control tools is a plus.
• IC Layout experience.
• LVS/DRC/ERC verification, troubleshooting, and debug skills.
• Proficiency in floor-planning activities with block assembly and block-level routing.
• Top-level IC layout experience and tape-out experience.

If you are interested and suited, please send your updated CV.